This invention pertains generally to systems, devices, and methods for polishing and planarizing semiconductor wafers, and more particularly to systems, devices, and methods utilizing multiple planarization pressure zones to achieving high-planarization uniformity across the surface of a semiconductor wafer.
As feature size decreases, density increases, and the size of the semiconductor wafer increase, Chemical Mechanical Planarization (CMP) process requirements become more stringent. Wafer to wafer process uniformity as well as intra-wafer planarization uniformity are important issues from the standpoint of producing semiconductor products at a low cost. As the size of dies increases a flaw in one small area increasing results in rejection of a relatively large circuit so that even small flaws have relatively large economic consequences in the semiconductor industry.
Many reasons are known in the art to contribute to uniformity problems. These include the manner in which wafer backside pressure is applied to the wafer during planarization, edge effect non-uniformities arising from the typically different interaction between the polishing pad at the edge of the wafer as compared to at the central region, and to non-uniform deposition of metal and/or oxide layers to might desirably be compensated for by adjusting the material removal profile during planarization. Efforts to simultaneously solve these problems have not heretofore been completely successful.
With respect to the nature of the wafer backside polishing pressure, hard backed heads were typically used. In many conventional machines, an insert is provided between the carrier (or subcarrier) surface and the wafer or other substrate to be polished or planarized in an attempt to provide some softness in an otherwise hard backed system. This insert is frequently referred to as the wafer insert. These inserts are problematic because they frequently result in process variation leading to substrate-to-substrate variation. This variation is not constant or generally deterministic. One element of the variation is the amount of water absorbed by the insert during a period of use and over its lifetime. Some process uniformity improvement may be achieved by initially soaking the insert in water prior to use. This tends to make the initial period of use more like the later period of use, however, unacceptable processes variations are still observed. These process variations may be controlled to a limited extend by preconditioning the insert with water as described and by replacing the insert before its characteristics change beyond acceptable limits.
Use of the insert has also required fine control of the entire surface to which the insert was adhered as any non-uniformity, imperfection, or deviation from planarity or parallelism of the subcarrier surface would typically be manifested as planarization variations across the substrate surface. For example, in conventional heads, an aluminum or ceramic plate would be fabricated, then lapped and polished before installation in the head. Such fabrication increases the costs of the head and of the machine, particularly if multiple heads are provided.
As the size of structures (feature size) on the semiconductor wafer surface have been reduced to smaller and smaller sizes, now typically about 0.2 microns, the problems associated with non-uniform planarization have increased. This problem is sometimes referred to as a Within Wafer Non-Uniformity (WIWNU) problem.
When so called hard backed planarization heads, that is heads that press the backside of the semiconductor wafer with a hard surface, the front surface of the wafer may not conform to the surface of the polishing pad and planarization non-uniformities may typically result. Such hard backed head designs generally utilize a relatively high polishing pressure (for example, pressure in the range between about 6 psi and about 8 psi) are used, and such relatively high pressures effectively deform the wafer to match the surface conformation of the polishing pad. When such wafer surface distortion occurs, the high spots are polished at the same time as the low spots give some degree of global uniformity but actually producing a bad planarization result. That is too much material from traces in some areas of the wafer will be removed and too little material from others. When the amount of material removed is excessive, those die or chips will not be useable.
On the other hand, when a soft backed head is used, the wafer is pressed against the polishing pad but as the membrane or other soft material does not tend to cause distortion of the wafer, lower polishing pressures may be employed, and conformity of the wafer front surface is achieved without distortion so that both some measure of global polishing uniformity and good planarization may be achieved. Better planarization uniformity is achieved at least in part because the polishing rate on similar features from die to die on the wafer is the same.
While some attempts have been made to utilize soft backed CMP heads, they have not been entirely satisfactory. In some head designs, there have been attempts to use a layer of pressurized air over the entire surface of the wafer to press the wafer during planarization. Unfortunately, while such approaches may provides a soft backed head it does not permit independent adjustment of the pressure at the edge of the wafer and at more central regions to solve the wafer edge non-uniformity problems.
With respect to correction or compensation for edge polishing effects, attempts have been made to adjust the shape of the retaining ring and to modify a retaining ring pressure so that the amount of material removed from the wafer near the retaining ring was modified. Typically, more material is removed from the edge of the wafer, that is the wafer edge is over polished. In order to correct this over polishing, usually, the retaining ring pressure is adjusted to be somewhat lower than the wafer backside pressure so that the polishing pad in that area was somewhat compressed by the retaining ring and less material was removed from the wafer within a few millimeters of the retaining ring. However, even these attempts were not entirely satisfactory as the planarization pressure at the outer peripheral edge of the wafer was only indirectly adjustable based on the retaining ring pressure. It was not possible to extend the effective distance of a retaining ring compensation effect an arbitrary distance into the wafer edge. Neither was it possible to independently adjust the retaining ring pressure, edge pressure, or overall backside wafer pressure to achieve a desired result.
With respect to the desirability to adjust the material removal profile to adjust for incoming wafer non-uniform depositions, few if any attempts to provide such compensation have been made.
Therefore, there remains a need for a soft backed CMP head that provides excellent planarization, controls edge planarization effects, and permits adjustment the wafer material removal profile to compensate for non-uniform deposition of the structural layers on the wafer semiconductor substrate.
The invention provides a polishing head and a polishing apparatus, machine, or tool (CMP tool) for polishing or planarizing a surface of a substrate or other work piece, such as a semiconductor wafer. The apparatus includes a rotatable polishing pad, and a wafer subcarrier which itself includes a wafer or substrate receiving portion to receive the substrate and to position the substrate against the polishing pad; and a wafer pressing member including a having a first pressing member and a second pressing member, the first pressing member applying a first loading pressure at an edge portion of the wafer against the polishing pad, and the second pressing member applying a second loading pressure a central portion of the wafer against the pad, wherein the first and second loading pressures are different. Although this wafer subcarrier and wafer pressing member may be used separately, in a preferred embodiment of the invention, the polishing apparatus further includes a retaining ring circumscribing the wafer subcarrier; and a retaining ring pressing member applying a third loading pressure at the retaining ring against the polishing pad. The first, second, and third loading pressures are independently adjustable.
In another aspect, the invention provides a method for planarizing a circular disc-type semiconductor wafer or other substrate. The method includes the steps of pressing a retaining ring surrounding the wafer against a polishing pad at a first pressure; pressing a first peripheral edge portion of the wafer against the polishing pad with a second pressure; and pressing a second portion of the wafer interior to the peripheral edge portion against the polishing pad with a third pressure. In another aspect, the second pressure may be provided through a mechanical member in contact with the peripheral edge portion; and the second pressure is a pneumatic pressure against a backside surface of the wafer. Desirably, the pneumatic pressure is exerted through a resilient membrane, or is exerted by gas pressing directly against at least a portion of the wafer backside surface.
In another aspect, the invention also provides a a subcarrier for a CMP apparatus that includes: a plate having an outer surface; a first pressure chamber for exerting a force to urge the plate in a predetermined direction; a spacer coupled to a peripheral outer edge of the plate; a membrane coupled to the plate via the spacer and separated from the plate by a thickness of the spacer; and a second pressure chamber defined between the membrane and the plate surface for exerting a second force to urge the membrane in a third predetermined direction.
In yet another aspect, the invention provides a carrier for a substrate polishing apparatus including: a housing; a retaining ring flexibly coupled to the housing; a first pressure chamber for exerting a first force to urge the retaining ring in a first predetermined direction relative to the housing; a subcarrier plate having an outer surface and flexibly coupled to the housing; a second pressure chamber for exerting a second force to urge the subcarrier plate in a second predetermined direction relative to the housing; the retaining ring circumscribing a portion of the subcarrier plate and defining a circular recess; a spacer coupled to a peripheral outer edge of the subcarrier plate outer surface within the retaining ring circular recess; a membrane coupled to the subcarrier plate via the spacer and disposed within the circular recess, the membrane separated from the subcarrier plate outer surface by a thickness of the spacer; and a third pressure chamber defined between the membrane and the outer subcarrier plate surface for exerting a third force to urge the membrane in a third predetermined direction relative to the housing.
The invention further includes a substrate, such as a semiconductor wafer, processed or fabricated according to the inventive method.